A general logics object.
It is assumed that the size of all ports are equal. The number of input ports and the size of the ports are decided by input parameters. This function supports the logical operations "and", "or" or "xor" (exclusive "or").
- Author
- Karl-Johan Reite
- Date
- 16.04.2007 KJR: Initial version.
-
20.07.2011 KGA: Ported to FhSim 2.0.
-
25.07.2011 KGA: Added documentation.
Example configuration excerpt
<Lib
LibName = "fhsim_base"
SimObject = "Math/Logic"
Name = "A"
Type = "xor"
PortWidth = "1"
NumInput = "2"
/>
...
<Connection
A.In1 = "1"
A.In2 = "0"
/>
Input Ports
Name | Width | Description |
In1 .. In<NumInput> | <PortWidth> | The input signal. |
Output Ports
Name | Width | Description |
Out | <PortWidth> | The result of the logical operation on the input. |
Configuration parameters
Name | Width | Description |
PortWidth | |
The number of elements in the input and output ports
|
Type | <PortWidth> | The logic operation applied to the input: "or" , "and" or "xor" |
NumInput | <PortWidth> |
The number of input ports
|
Initial conditions
This SimObject contains no initial conditions.
Full example file
<Contents>
<OBJECTS>
<Lib
LibName="base"
SimObject="Math/Logic"
Name="A"
Type="OR"
/>
<Lib
LibName="base"
SimObject="Math/Logic"
Name="B"
Type="AND"
/>
<Lib
LibName="base"
SimObject="Math/Logic"
Name="C"
Type="XOR"
/>
</OBJECTS>
<INTERCONNECTIONS>
<Connection
A.In1="0"
A.In2="1"
B.In1="1"
B.In2="1"
C.In1="1"
C.In2="1"
/>
</INTERCONNECTIONS>
<INITIALIZATION>
<InitialCondition
/>
</INITIALIZATION>
<INTEGRATION>
<Engine
IntegratorMethod="2"
NumCores="1"
TOutput="0, 1, 30"
LogStates ="1"
stepsize ="0"
HMax="0.002"
HMin="0.00000001"
AbsTol="1e-3" RelTol="1e-3"
UseRSSNormInsteadOfInfNorm="0"
FileOutput="objects:all"
/>
</INTEGRATION>
</Contents>
This SimObject is referred to as Math/Logic